1. Field of the Invention
The present invention relates to multiple processors in computer systems, and more particularly to communication between multiple processors using reduced addressing lines.
2. Description of the Prior Art
The personal computer industry is a vibrant and growing field that continues to evolve as new innovations occur. The driving force behind this innovation has been the increasing demand for faster and more powerful personal computers. In order to meet this demand, computer designers have used various methods to increase the speed with which personal computers can process instructions. Historically, the personal computer has developed as a system utilizing a single microprocessor to handle all instruction execution. The microprocessor is the key working unit or "brains" of the personal computer, and its task is to handle all of the instructions that programs give it in the form of computer software.
One method that is being used to increase the speed of the personal computer is the incorporation of multiple microprocessors operating in parallel into a computer system. With the use of multiple processors, or multiprocessing, each microprocessor can be working on a different task at the same time. Systems that incorporate multiprocessing generally use standard microprocessors that operate off of a common bus and share a common memory. The use of multiprocessing has generally increased computer performance, but it has also introduced new design considerations that were not found in a single processor environment.
One consideration that arises in multiprocessing is how to allow the processors to communicate with each other. Communication between the processors in a multiprocessor system is generally necessary for the proper functionality of the system. One method that has been used for multiprocessor communication includes the use of input/output (I/O) registers which enable the processors to pass messages back and forth. The use of I/O registers, however, has conventionally required an address decode using a large number of address and control signals. In computer systems that utilize a 32-bit address bus, this decode may generally include a 16-bit address decode for I/O mapped registers and a 32-bit address decode for memory mapped registers. It would be desirable to locate the communication registers on the local bus to minimize the time spent by each of the processors on interprocessor communication. However, the address decoding requirements hamper this effort because the resultant loading affects are obtrusive on overall system performance. If other address lines are used, they are generally not available on a card containing the microprocessor if the microprocessor is located on an interchangeable card which allows simple replacement of the microprocessors used in the computer system. Thus the 16-bit or 32-bit address lines and additional control signals necessary for the decode must be provided to the card, which may result in an unnecessarily large pin count of the connector used with the card.